ip stresser

Abhilash G.

Education Details:

  • M.Tech – Signal Processing
  • BE – Electronics and Communication

Contact Details

Email ID ABHILASHG_EC@atme.edu.in
LinkedIn ID https://www.linkedin.com/in/abi7ash/
Google Scholor  ID https://scholar.google.com/citations?user=PSW9od8AAAAJ&hl=en
Orcid ID https://orcid.org/0000-0003-1215-398X
Vidwaan ID https://vidwan.inflibnet.ac.in/profile/201920
Scopus ID

Professional Experience

  • Teaching Experience: 11 yrs

Publication Details:

  • Chandra Shekar P and Abhilash G “ Design of 64 X 64 single port SRAM Array Using 45nm Technology” Published a paper in ICRTST-2020 ISSN No. 978-93-5396-830-4 issue 1 vol. 1 page 64
  • Survey of CMOS 45nm based Fractional-N Phase Lock Loop, Abhilash G, Rohan Pavaskar, Rakshan C, April 2019,National Conferece on Communication and Data Science-NCCDS 2019, Dept of ECE, GSSSIETW, Mysuru
  • Cadence based implementation of Successive Approximation ADC using 45nm cmos technology, Umamaheshwari P R Abhilash G, Chaithanya Lakshmi S, Elayaraju V, 2017/July,INTERNATIONAL CONFERENCE ON SIGNAL, IMAGE PROCESSING, COMMUNICATION & AUTOMATION (ICSIPCA- 2017), Pages 191-196, 02.MH-ICSIPCA.2017.1.29
  • Generation of Different Amplitude Modulated Signals using MATLAB Simulink, Abhilash G Ashwini B N, Shruthi S Prabhu, June 2017, Journal International journal of Radio, Space and Aerospace Engineering, Volume 2, Issue 2, Page 1-16, MANTECH PUBLICATIONS 2017
  • Successive Approximation Register ADC using 45nm CMOS Technology, Elayaraju V Abhilash G, Chaithanya Lakshmi S, Umamaheshwari P R, May 2017, Conference International Conference on Emerging Trends in Science & Engineering ICETSE – 2017, Coorg Institute of Technology, Ponnampet, S. Kodagu, Karnataka, India

Roles and Responsibility

  • VLSI Training Coordinator and Training on VLSI Physical Design
  • Member of Teaching and Learning Process and Classroom teaching evaluation Committee
  • Member of Cultural Committee
  • Internship and Training

Professional body membership

  • International Society for Research and Development (ISRD)
  • International Association of Engineers (IAENG)
  • Member of Indian Society for Technical Education (MISTE)

FDP/Conferences/Workshops attended/Conducted

  • Participated in three day FDP on “Intellectual Property Rights in Engineering Educations” from 29th to 31st July 2020 organized by ATMECE, Mysuru in association with KSCST, IIsc Campus, Bengaluru
  • A four days VTU-VGST FDP on Virtual Instrumentation Essentials for Academic and Research in Engineering, from 28-05-2014 to 31-05-2014 by Adichunchangiri Institute of Technology, Chikmagalur.
  • A Five days FDP on “GNU Radio and Software Defined Radio” by JSS Academy of Technical Educatin, Bengaluru in association with Tent Technetronics, Bengaluru from 27th June – 1st July 2016.
  • Organized A six days Faculty Development Program on “Network Simulator-3” held from 12th – 17th December 2016 at ATMECE Mysuru
  • participated in the “One day Workshop on eSim, a First Course in the IoT Series for Teachers” held at ATME College Of Engineering on 21 September 2019, organised by the Teaching Learning Centre ICT at IIT Bombay, funded by the Pandit Madan Mohan Malaviya National Mission on Teachers and Teaching (PMMMNMTT), MHRD, Govt. of India
  • Attended the Python Workshop on 22th June 2019, at ATMECE, the Teaching Learning Centre ICT at IIT Bombay, funded by the Pandit Madan Mohan Malaviya National Mission on Teachers and Teaching (PMMMNMTT), MHRD, Govt. of India
  • Organized in three days FDP on “Importance of NAAC Accreditation in Higher Education Institutions” from 9-11-2020 to 11-11-2020
  • Participated in three-day National Level Online FDP on “AICTE exam Reforms – An Overview” from 27th to 29th August 2020.

Paper Publications:
National Conference: 3
International Conference: 3

National Journal Publication: –

  • International Journal Publication: 1

Research Area of Interest

  • Analog VLSI Design
  • VLSI Design and Verification
  • Networking and Linux
  • Embedded Systems Design

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